Toward a Memory-Centric, Stacked Architecture for Extreme-Scale, Data-Intensive Computing

One of the primary concerns of performing efficient data-intensive computing at scale is the inherent ability to exploit memory bandwidth on a local and global scale. The traditional computer architecture inherently decouples the processing interconnect from the memory interconnect, thus preventing efficient, parallel utilization of both at scale. Further, the orthogonal nature of these board-level and systemlevel interconnects force users to build messaging libraries to bridge the gap between local and global memory access. The result is a system architecture that fails to efficiently expose the necessary locality of non-deterministic data patterns for algorithmic exploitation at scale. In this position paper, we present a theoretical architecture based upon processing near memory using a 3-dimensional stacked device component as the central processing and networking component. We utilize the second generation, Hybrid Memory Cube device architecture, packet specification and interconnect as the basis for our architecture in order to dramatically increase the compute-to-bandwidth relationship by augmenting the logic layer of the HMC devices with actual processing elements. We also utilize the same core component to serve as the interconnection mechanism between multiple processing elements such that memory and communication become a homogeneous function of the platform. Finally, we explore two potential algorithmic exploitation methodologies that could be used to efficiently implement non-deterministic data analytics problems at scale.